From sd.israr at gmail.com  Sun Nov 17 10:46:00 2019
From: sd.israr at gmail.com (Israr Sayed)
Date: Mon, 18 Nov 2019 00:16:00 +0530
Subject: [Clfs-dev] Why No MMU/No ARM Iinstruction Set Architectures
 mentioned in [4.3. Build Variables ].
Message-ID: <20191117184600.GA6150@hib>

As far as Cortex-R and Cortex-M are concerned , they are MMU less devices.
They are not having ARM Instruction Set.Whereas Libgcc , expects both.
Those Devices should not be build for OS based GCC build. If somehow they got build, they wont be working.
It is kind of misleading.They should be mentioned seperately for Bare Metal and Linux based configure. 
I have discussed this in GCC ML.https://gcc.gnu.org/ml/gcc-help/2019-11/msg00026.html.

From sd.israr at gmail.com  Sun Nov 17 10:46:00 2019
From: sd.israr at gmail.com (Israr Sayed)
Date: Mon, 18 Nov 2019 00:16:00 +0530
Subject: [Clfs-dev] Why No MMU/No ARM Iinstruction Set Architectures
 mentioned in [4.3. Build Variables ].
Message-ID: <20191117184600.GA6150@hib>

As far as Cortex-R and Cortex-M are concerned , they are MMU less devices.
They are not having ARM Instruction Set.Whereas Libgcc , expects both.
Those Devices should not be build for OS based GCC build. If somehow they got build, they wont be working.
It is kind of misleading.They should be mentioned seperately for Bare Metal and Linux based configure. 
I have discussed this in GCC ML.https://gcc.gnu.org/ml/gcc-help/2019-11/msg00026.html.


From sd.israr at gmail.com  Sun Nov 17 10:46:00 2019
From: sd.israr at gmail.com (Israr Sayed)
Date: Mon, 18 Nov 2019 00:16:00 +0530
Subject: [Clfs-dev] Why No MMU/No ARM Iinstruction Set Architectures
 mentioned in [4.3. Build Variables ].
Message-ID: <20191117184600.GA6150@hib>

As far as Cortex-R and Cortex-M are concerned , they are MMU less devices.
They are not having ARM Instruction Set.Whereas Libgcc , expects both.
Those Devices should not be build for OS based GCC build. If somehow they got build, they wont be working.
It is kind of misleading.They should be mentioned seperately for Bare Metal and Linux based configure. 
I have discussed this in GCC ML.https://gcc.gnu.org/ml/gcc-help/2019-11/msg00026.html.